Astables
A counter needs something to count. An astable circuit is the answer: a circuit with no stable output state at all, endlessly flipping between high and low all on its own, producing exactly the steady stream of pulses a counter's clock input needs to drive it.
A circuit with no stable state
Most circuits settle. Given a fixed set of inputs, they reach some steady output and stay there until an input changes. An astable circuit is the deliberate exception: it has no stable output state whatsoever. Left alone, with no external trigger of any kind, it continuously oscillates between its high and low output levels all by itself, producing an endless repeating stream of pulses.
This makes an astable ideally suited to one specific job: acting as a clock source. The previous lesson introduced counters as circuits that advance one step every time a pulse arrives on their clock input — but that clock input has to get its pulses from somewhere. An astable, left running continuously, is exactly the kind of self-sustaining pulse generator that can be wired directly into a counter's clock input to drive it.
As with the gates covered earlier in this topic, no specific chip's internal circuitry is required knowledge here — you don't need to know how any particular astable chip achieves this oscillation internally. What matters for this course is describing and characterising the astable's output waveform, and understanding how its timing can be controlled from outside the chip.
Describing the output waveform
An astable's output is a repeating square-wave-like trace: it snaps high, stays high for some time, snaps low, stays low for some time, then repeats indefinitely. Several precise terms describe this waveform.
- Pulse rate / frequency. The number of complete cycles occurring per second, measured in hertz.
- Period, $T$. The time taken for one complete cycle — the high time plus the low time together. Frequency and period are reciprocals of one another.
- Pulse width. The duration the output stays in its "high" (on) state during each cycle.
- Duty cycle. The fraction of each period spent high, usually expressed as a percentage.
- Mark-to-space ratio. The ratio of "on" time to "off" time within each cycle, written mark:space — a slightly different way of expressing the same high/low timing balance as duty cycle.
Varying the frequency with an external RC network
An astable's output frequency isn't fixed by the astable circuit alone — it's set by an external RC (resistor-capacitor) network connected to the circuit. Inside each cycle, a capacitor in this network charges and discharges through one or more resistors, and the rate at which it does so is governed by the RC time constant of that network. This charge/discharge timing directly sets the pulse width and period of the output, so changing the value of the resistor(s) or capacitor changes the output frequency — and, depending on the specific circuit topology, can also change the duty cycle.
- A larger resistance or capacitance means the capacitor takes longer to charge and discharge each cycle, stretching out the period and lowering the frequency.
- A smaller resistance or capacitance means faster charging and discharging, shortening the period and raising the frequency.
An astable's operating frequency is not some fixed property of the chip itself — it's a design choice, made by the engineer selecting appropriate external resistor and capacitor values for the RC network. The same astable circuit can be made to oscillate anywhere from a slow, visibly blinking rate to a fast clock signal suitable for driving a counter, purely by choosing different external R and C components.
Key takeaways
- An astable circuit has no stable output state — it oscillates continuously between high and low with no external trigger needed.
- Its main practical role is as a clock source, driving the clock input of a counter (linking directly to the previous lesson).
- No specific chip's internal circuitry is required knowledge — the focus is the output waveform and its external timing control.
- Period $T$ is the time for one complete cycle; frequency $f = 1/T$ is the number of cycles per second.
- Pulse width is the time spent high in each cycle; duty cycle is pulse width as a percentage of the period; mark-to-space ratio expresses the same high:low balance as a ratio.
- An external RC network sets the timing: the capacitor's charge/discharge rate through the resistor(s) directly determines pulse width and period.
- Changing the resistor or capacitor values changes the output frequency, and potentially the duty cycle, depending on the circuit topology.
- Across this topic: gates (stateless building blocks) → designing circuits (truth tables ↔ gate networks, including NAND-only builds) → counters (circuits with memory stepping through a state sequence) → astables (self-oscillating clock sources driving that stepping) — together, the complete toolkit for a real digital timing/counting system.